Peer-Reviewed Journal Details
Mandatory Fields
Cowley, A;Ivankovic, A;Wong, CS;Bennett, NS;Danilewsky, AN;Gonzalez, M;Cherman, V;Vandevelde, B;De Wolf, I;McNally, PJ
Microelectronics and Reliability
B-Spline X-Ray Diffraction Imaging - Rapid non-destructive measurement of die warpage in ball grid array packages
3 ()
Optional Fields
Next generation "More than Moore" integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging ( [1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 mu m, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die. This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice mis-orientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 mu rad approximate to 0.003 degrees in times as short as 9-180 s (worst case X-Y spatial resolution = 100 mu m) for a full 8.7 mm x 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package. (C) 2016 Elsevier Ltd. All rights reserved.
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