This paper discusses the effects of residual structural crystal defects in the GaAs metal-semiconductor held effect transistor (MESFET) on device electrical performance, in particular piezoelectrically-active defect-induced d.c. threshold voltage shifts due to the presence of these defects.
It has been known for some time that particular defect structures (i.e. edge and 60 degrees types) produce a piezoelectrically-induced polarization vector in the non-centrosymmetric GaAs lattice, giving rise to distributions of equivalent piezoelectric charge in the vicinity of these defects.
This study proves conclusively that such piezoelectrically-active defects have a definite effect on the d.c. electrical performance of a GaAs MESFET. For this study a device gate length of 1 mu m was used and the various defects were positioned at chosen locations in and around the gate-substrate interface. The respective modelled threshold voltage shifts (Delta V-T) associated with the edge and 60 degrees types of crystal dislocations in GaAs semiconductor are calculated utilizing a simple 1-dimensional calculation of the moment arm of the induced charge distribution along a line mid-way between the centre and the edge of the gate. Such calculations have shown that the maximum Delta Y-T due an edge-type defect located mid-way between the gate centre and the gate edge is of magnitude 13.7 mV: for the 60 degrees-type the maximum Delta V-T is of magnitude 11.5 mV. In fact, there are two types of edge and 60 degrees defects, known as ct and beta types, the induced V-T shifts of which are of opposite polarity, but similar in all other respects.
Previous studies, involving the application of real stresses to GaAs MESFETs to study the effects of processing over-layer stresses, noted an anomalous effect wherein the observed V-T shifts were of the order of 10-15 mV for approximately 7% of the tested devices. The suggested cause of such voltage shifts was the presence of stress-induced piezoelectrically-active defects as opposed to the more 'normal' and better understood mechanism of overlayer stress-induced piezoelectric effects. The results obtained in this study show, for the first time, that the presence of a piezoelectric defect located in or near the active channel of a GaAs MESFET, will affect the threshold voltage of the device in a region close to the centre of the defect. Furthermore, they can very easily account for previous experimental observations. Combining this previous experimental data with the results of the present study, there is now strong evidence to suggest that the piezoelectric attributes of defects in a GaAs substrate cannot be ignored in any medium- or large-scale device integration technology.