This study focuses on using synchrotron x-ray topography to study fully processed silicon wafer lots with varying, though, low average yields. The electrical circuits were fabricated in a mixed-signal complementary metal-oxide semiconductor (CMOS) process. Synchrotron x-ray section topographs are analysed with image processing software written entirely for this study. The software reduces image data by encoding the relevant factors into curve feature parameters, in order to quantify the strain gradients and defect factors present in the images. This information is then correlated against the integrated circuit process control monitoring (PCM) data and the yield, i.e. the electrical semiconductor process parametric values of the wafers. Several image features extracted from the synchrotron x-ray topographs show a strong correlation with certain PCM parameters, e.g. PMOS transistor threshold voltage, polysilicon sheet resistance and N-contact chain sheet resistance, rather than with others, e.g. NMOS breakdown voltage. A positive correlation between good yield and strong near-surface strain gradient is found.