McNally, PJ;Rantamaki, R;Tuomi, T;Danilewsky, AN;Lowney, D;Curley, JW;Herbert, PAF

2001

March

IEEE Transactions on Components and Packaging Technologies

Mapping of mechanical, thermomechanical and wire-bond strain fields in packaged Si integrated circuits using synchrotron white beam x-ray topography

Published

7 ()

DIFFRACTION TOPOGRAPHY PLASTIC PACKAGES MOLD COMPOUNDS CHIP SURFACE STRESS PHOTOELASTICITY RELIABILITY RADIATION DEFECTS

24

76

83

Thermal processing steps used during the production of packaged integrated circuits can lead to severe thermomechanical stresses. In addition, the process of bonding wires to contact pads can also lead to strain field generation. A feasibility study using the application of white beam synchrotron x-ray topography to packaged erasable programmable read-only memory (EPROM) Si integrated circuits (ICs) has been undertaken in order to produce maps of the strain fields induced by such processing steps. This technique provides depth-resolved mapping with spatial-resolutions currently in the region of 5-10 mum throughout the entire mapping volume. Furthermore, the use of different experimental geometries allows the user to nondestructively probe the strain fields present at the wafer surface right through to the back side.

NEW YORK

1521-3331