The control and characterisation of wafer defect and strain distributions is of crucial importance for the development of advanced Ultra Large Scale Integration (ULSI) circuits. Within the IC manufacturing sector 0.35 mu m linewidth-based advanced Complementary Metal Oxide Semiconductor (CMOS) logic has recently emerged at a high level of maturity, to be closely followed by an even more demanding 0.25 mu m process. One very important issue is the need to ensure a uniform, high quality Si substrate, i.e. minimise defect densities and eliminate strain distributions in the starting wafer material. Synchrotron section and back-reflection topographic techniques were applied to 200 mm diameter p-Si wafers, upon which, boron and arsenic doped epitaxial silicon layers had been deposited. These wafers were supplied from manufacturers around the globe and revealed substantial differences in the overall quality of the epilayers and substrates. In all wafers the substrate quality varied significantly with position across the wafer, as measured by the presence of oxygen-related defects and dopant strain homogeneity. The strain field uniformity, induced by the growth of lightly doped Si epilayers, was also observed to vary qualitatively with location on a wafer. Back-reflection topographs verify that the quality of the epilayer-substrate interface improved as the thickness of the epilayer, or the gradient of dopant density across the interface, is reduced. Cellular strain-related structures, of the order of a few hundred mu m in circumference, have been observed in the more stressed p on p(+) samples. Topographic results are in agreement with those obtained from X-ray diffraction measurements. Finally, an examination was carried out into the quality of commercially supplied 200 mm diameter Si wafers, revealing differences in the overall quality of the wafers. (C) 1999 Elsevier Science B.V. All rights reserved.